7680x4320@48fps Motion Estimation Processor Chip

SMIC 40nm CMOS, 2.458M logic gates/ 552kB on-chip memory
64b + 32b DDR3 DRAM interface
622mW @ 210MHz(core)/420MHz(DDR3) for max. perf.

Max. -211-to-211 search range, P & B frames supported
16x16, 16x8, 8x16 and 8x8 integer motion estimation
H.264/AVC and H.265/HEVC compatible fractional motion estimation

J. Zhou, D.Zhou, et al., Symposium on VLSI Circuits, 2013 [paper] 

D.Zhou, J.Zhou, et al., IEEE Journal of Solid-State Circuits, 2014. [paper]
 

7680x4320@60fps H.264/AVC HP/MVC Decoder Chip

SMIC 65nm CMOS, 4x4mm2, 1.2V core, 176-pin LQFP

1338K logic gates/ 79.9kB on-chip memory
410mW @340MHz(core)/400MHz(DRAM), 7680x4320@60fps
64b DDR2 external memory

D.Zhou, J.Zhou, et al., International Solid-State Circuits Conference (ISSCC), 2012 [paper]

J.Zhou, D.Zhou, et al., IEEE Transactions on VLSI Systems (TVLSI), 2015. [paper]

4096x2160@60fps H.264/AVC Video Decoder Chip

SMIC 90nm CMOS, 4x4mm2, 1.0V core, 176-pin LQFP

662K logic gates/ 59.6kB on-chip memory
189mW @175MHz, 4096x2160@60fps
64b LPDDR external memory

D.Zhou, J.Zhou, et al., Symposium on VLSI Circuits, 2010 [paper]
D.Zhou, J.Zhou, et al., IEEE Journal of Solid-State Circuits, 2011 [paper]

Related papers

  • Jinjia Zhou, Dajiang Zhou, Satoshi Goto, "100x Evolution of Video Codec Chips," 2017 ACM on International Symposium on Physical Design (ISPD 2017), pp. 121-122, Portland, Oregon, USA, March 2017.

  • Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto, "A 7-Die 3D Stacked 3840x2160@120 fps Motion Estimation Processor," IEICE Transactions on Electronics, Vol. E100-C, No.3, pp. 223-231, March 2017

  • Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto, "An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design," IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 1, pp. 113 - 126, Jan. 2017.

  • Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, and Satoshi Goto, "A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H. 265/HEVC," IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 2016.

  • Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, and Satoshi Goto, "A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 266-267, February 2016.

  • Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, and Satoshi Goto, "A frame-parallel 2G pixel/s video decoder chip for UHDTV and 3DTV/FTV applications," IEEE Transactions on VLSI Systems (TVLSI), Vol. 23, No. 12, pp. 2768-2781, December 2015.

  • Dajiang Zhou, Jinjia Zhou, Wei Fei, and Satoshi Goto, "Ultra-high-throughput VLSI architecture of H.265/HEVC CABAC encoder for UHDTV applications," IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Vol. 25, No. 3, pp. 497-507, March 2015

  • Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, and Satoshi Goto, "Low-power Motion Estimation Processor with 3D Stacked Memory," IEICE Transactions on Fundamentals, Vol. E98-A, No. 7, pp. 1431-1441, July 2015.

  • Jinjia Zhou, Dajiang Zhou, and Satoshi Goto, "A Fixed-Complexity HEVC Inter Mode Filtering Algorithm Based on Distribution of IME-FME Cost Ratio," IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, pp. 617-620, May 2015.

  • Shuping Zhang, Jinjia Zhou, Dajiang Zhou, and Satoshi Goto, "A low power 720p motion estimation processor with 3D stacked memory," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Mexico, pp. 237-242, October 2014.

  • Yijin Zhao, Jinjia Zhou, Dajiang Zhou and Satoshi Goto, "A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications," IEEE International Conference on Image Processing (ICIP), Paris, France, October 2014.

  • Dajiang Zhou, Li Guo, Jinjia Zhou, and Satoshi Goto, "Reducing power consumption of HEVC codec with lossless reference frame recompression," IEEE International Conference on Image Processing (ICIP), Paris, France, October 2014. Top 10% Paper Award.

  • Jinjia Zhou, Dajiang Zhou, and Satoshi Goto, "Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC," Journal of Visual Communication and Image Representation (JVCI), 2014.

  • Dajiang Zhou, Jinjia Zhou, Gang He, and Satoshi Goto, "A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 4, pp. 827-837, April 2014.

  • Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou, and Satoshi Goto, "High-performance H.264/AVC intra prediction architecture for ultra high definition video applications," IEEE Transactions on VLSI Systems (TVLSI), Vol. 22, No. 1, pp. 76-89, January, 2014.

  • Jinjia Zhou, Dajiang Zhou, Wei Fei, and Satoshi Goto, "A high-performance CABAC encoder architecture for HEVC and H.264/AVC," IEEE International Conference on Image Processing (ICIP 2013), Melbourne, Australia, September 2013.

  • Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, and Satoshi Goto, "A dual-mode deblocking filter design for HEVC and H.264/AVC," IEICE Transactions on Fundamentals, Vol. E96.A, No. 6, pp. 1366-1375, June 2013.

  • Jinjia Zhou, Dajiang Zhou, Gang He, and Satoshi Goto, "A 1.59Gpixel/s motion estimation processor with -211-to-211 search range for UHDTV video encoder," Symposium on VLSI Circuits (VLSIC 2013), Kyoto, Japan, pp. 286-287, June, 2013.

  • Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, and Satoshi Goto, "A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS," Asia and South Pacific Design Automatio Conference (ASP-DAC 2013), Vol. 2, Yokohama, Japan, pp. 73-74, January, 2013, University Design Contest Finalist.

  • Muchen Li, Jinjia Zhou, Xiao Peng, Dajiang Zhou, and Satoshi Goto, "De-blocking filer design for HEVC and H.264/AVC," Pacific Rim Conference on Multimedia (PCM 2012), Singapore, December 2012

  • Jinjia Zhou, Dajiang Zhou, and Satoshi Goto, "Interlaced asymmetric search range assignment for bidirectional motion estimation," IEEE International Conference on Image Processing (ICIP 2012), Orlando, USA, pp. 1557-1560, September 2012.

  • Gang He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder," European Signal Processing Conference (EUSIPCO 2012), Bucharest, Romania, pp. 1054-1058, August 2012.

  • Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, and Satoshi Goto, "A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC,"  Symposium on VLSI Circuits (VLSIC 2012), Honolulu, USA, pp. 154-155, June 2012.

  • Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, and Satoshi Goto, "A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications," IEEE International Solid-State Circuits Conference (ISSCC 2012), San Francisco, USA, pp. 224-226, February, 2012.

  • Jinjia Zhou, Dajiang Zhou, Gang He, and Satoshi Goto, "A 16-65 cycles/MB H.264/AVC motion compensation architecture for quad-HD applications," European Signal Processing Conference (EUSIPCO 2011), Barcelona, Spain, pp. 728-733, August 2011.

  • Gang He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "A 530Mpixels/s intra prediction architecture for ultra high definition H.264/AVC encoder," IEICE Transactions on Electronics, Vol. E94-C, No. 4, pp. 419-427, April 2011.

  • Jinjia Zhou, Dajiang Zhou, Gang He, and Satoshi Goto, "Cache based motion compensation architecture for quad-HD H.264/AVC video decoder," IEICE Transactions on Electronics, Vol. E94-C, No. 4, pp. 439-447, April 2011.

  • Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, and Satoshi Goto, "A 530 Mpixels/s 4096x2160@60fps H.264/AVC high profile video decoder chip," IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 4, pp. 777-788, April, 2011.

  • Gang He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "Intra prediction architecture for H.264/AVC QFHD encoder," Picture Coding Symposium (PCS 2010), Nagoya, Japan, pp. 450-453, December 2010.

  • Jinjia Zhou, Dajiang Zhou, Gang He, and Satoshi Goto, "A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding," Pacific Rim Conference on Multimedia (PCM 2010), Shanghai, China, pp. 52-61, September 2010.

  • Jinjia Zhou, Dajiang Zhou, Xun He, and Satoshi Goto, "A bandwidth optimized, 64 cycles/MB joint parameter decoder architecture for ultra high definition H.264/AVC applications," IEICE Transactions on Fundamentals, Vol. E93-A, No. 8, pp. 1425-1433, August 2010.

  • Xun He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "High profile intra prediction architecture for UHD H.264 decoder," IPSJ Transactions on System LSI Design Methodology, Vol. 3, No. 2, pp. 303-313, August 2010.

  • Dajiang Zhou, Jinjia Zhou, Xun He, Ji Kong, Jiayi Zhu, Peilin Liu, and Satoshi Goto, "System-level low power design for ultra high definition H.264/AVC video decoder," ACM International Symposium on Low Power Electronics and Design (ISLPED 2010), Austin, USA, August, 2010, Design Contest Award 3rd Place.

  • Dajiang Zhou, Jinjia Zhou, Xun He, Ji Kong, Jiayi Zhu, Peilin Liu, and Satoshi Goto, "A 530Mpixels/s 4096x2160@60fps H.264/AVC high profile video decoder chip,"  Symposium on VLSI Circuits (VLSIC 2010), Honolulu, USA, pp. 171-172, June, 2010, Best Student Paper Award.

  • Jinjia Zhou and Satoshi Goto, "Efficient VLSI architectures for ultra high definition H.264/AVC deblocking filter," Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Student Forum, Taipei, Taiwan, Jan. 2010.

  • Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, and Satoshi Goto, "A 48 cycles/MB H.264/AVC deblocking filter architecture for ultra high definition applications," IEICE Transactions on Fundamentals, Vol. E92-A, No. 12, pp. 3203-3210, December 2009.

  • Jinjia Zhou, Dajiang Zhou, Xun He, and Satoshi Goto, "A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications," ISPACS 2009, Kanazawa, Japan, pp. 49-52, December 2009.

  • Xun He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "A new architecture for high performance intra prediction in H.264 decoder," ISPACS 2009, Kanazawa, Japan, pp. 41-44, December 2009.

  • Jinjia Zhou, Dajiang Zhou, Xun He, and Satoshi Goto, "A high speed deblocking filter architecture for H.264/AVC,"
    ISOCC 2009, Busan, Korea, pp. 63-66, November 2009, invited special session paper.

  • Xun He, Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "High profile intra prediction architecture for H.264," ISOCC 2009, Busan, Korea, pp. 57-60, November 2009, invited special session paper.

  • Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "An efficient motion vector coding scheme based on prioritized reference decision," IEICE Transactions on Fundamentals, Vol. E92-A, No. 8, pp. 1978-1985, August 2009.

  • Dajiang Zhou, Zongyuan You, Jiayi Zhu, Ji Kong, Yu Hong, Xianmin Chen, Xuewen He, Chen Xu, Hang Zhang, Jinjia Zhou, Ning Deng, Peilin Liu, and Satoshi Goto, "A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective," Symposium on VLSI Circuits (VLSIC 2009), Kyoto, Japan, pp. 262-263, June, 2009.

  • Jinjia Zhou, Dajiang Zhou, Hang Zhang, Yu Hong, Peilin Liu, and Satoshi Goto, "A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications," IEEE International Conference on Multimedia and Expo (ICME 2009), NYC, USA, pp. 1134-1137, June 2009.

  • Dajiang Zhou, Jinjia Zhou, and Satoshi Goto, "Prioritized reference decision for efficient motion vector coding," IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan, pp. 1649-1652, May 2009.

Address: W6036, 3-7-2 Kajino, Koganei, Tokyo 184-8584, Japan.

Tel:+ 042 387 6363

Email:jinjia.zhou.35 athosei.ac.jp