Profile

Jinjia Zhou (周 金佳/しゅう きんか) received B.E. degree from Shanghai Jiao Tong University, China, in 2007. She received M.E. and Ph.D. degrees from Waseda University, Japan, in 2010 and 2013, respectively. From 2013 to 2016, she was a junior researcher with Waseda University, Fukuoka, Japan. Currently, she is an Associate Professor and a co-director of the English based graduate program at Hosei University. She is also a senior visiting scholar in State Key Laboratory of ASIC & System, Fudan University, China. From 2020, She is also a specially appointed Assoc. Prof. with Osaka University. Her interests are in algorithms and VLSI architectures for multimedia signal processing.

Dr. Zhou was selected as JST PRESTO researcher during 2017-2021. She received the research fellowship of the Japan Society for the Promotion of Science during 2010-2013. Dr. Zhou is a recipient of the Chinese Government Award for Outstanding Students Abroad of 2012. She received the Hibikino Best Thesis Award in 2011. She was a co-recipient of ISSCC 2016 Takuo Sugano Award for Outstanding Far-East Paper, the best student paper award of VLSI Circuits Symposium 2010, and the design contest award of ACM ISLPED 2010. She participated in the design of the world-first 8K UHDTV video decoder chip, which was granted the 2012 Semiconductor of the Year Award of Japan.

 

She works as an associate editor for IEEE Access, an editorial board member for Cognitive Robotics, and as a reviewer for journals including IEEE Trans. Circuits Syst. Video Tech., IEEE Trans. Circuits Syst. I, IEEE Trans. VLSI Syst., and IEEE Trans. Multimedia.

Jinjia Zhou / 周 金佳

Associate Professor, Ph.D.

Award and Honors

  • 2020 Best Paper Runner-up Award of the 26th International Conference on Multimedia Modeling (MMM)

  • 2017 ISSCC 2016 Takuo Sugano Award for Outstanding Far-East Paper.

  • 2014 ICIP Top 10% Paper Award

  • 2013 STARC Symposium Best Presentation Award

  • 2012 Chinese Government Award

  • 2012 "Semiconductor of the Year" Award of Semiconductor Industry News

  • 2011 Hibikino Best Master Thesis Award 

  • 2010 JSPS Research Fellowship for Young Scientists

  • 2010 International Low Power Design Contest Award of ACM ISLPED

  • 2010 Best Student Paper Award of VLSI Circuits Symposium

  • 2009 Isao Okawa Information and Communication Academic Scholarship

  • 2008 Global COE Research Fellowship

  • 2006 Toshiba Scholarship for SJTU Student

Academic Activities

Session Chair: The International Symposium on Physical Design (ISPD) 2017

TPC Member: The International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2018. 

Program Chair of High-Performance Computing and Computational Intelligence (HPCCI) 2020; Technical Committee of International Conference on Image and Video Processing (ICIVP) 2020.

Associate Editor: IEEE Access

Reviewer: IEEE Access, IEEE TCSVT, IEEE TVLSI, IEEE TCAS II, IEEE TMM, etc. 

Address: W6036, 3-7-2 Kajino, Koganei, Tokyo 184-8584, Japan.

Tel:+ 042 387 6363

Email:jinjia.zhou.35 athosei.ac.jp